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Welcome to my blog! This is where I collect my observations and notes on programming and technology. The main subjects range from implementation details to broader ideas about programming.
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- Engineering Projects: Exploring implementation details and how technical systems work.
- C/C++: Notes on language features and programming techniques.
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Points to Keep in Mind
When installing or copying a routine, check the size of the destination’s safe memory region as well as the size of the code being copied. With instructions such as MOVSB, pay attention to the count in CX and the length of the target program.
For an interrupt routine that will be copied to a different address, relative control transfers are particularly useful. Labels used in other address expressions need careful relocation handling; an address assembled for the original location may be wrong after the copy.
When one interrupt handler invokes another routine, decide which register values must be preserved. Some fatal conditions intentionally return to the system rather than resume the interrupted program, so their preservation requirements differ.
For ordinary subroutines, the calling convention determines what must be saved. Registers carrying return values must expose those values to the caller rather than have them overwritten by restoration. Registers used internally but promised unchanged to the caller should be saved and restored.
Modularity is especially important in assembly programming. Keep modules loosely coupled and give them clear responsibilities. This reduces the debugging and testing burden and improves readability, robustness, and maintainability.
One Last Encoding Observation
A far pointer is commonly written in machine-code storage with its offset before its segment. The original notes associate this ordering with instruction decoding and the prevalence of transfers within a segment. It is best treated as an encoding convention to verify in the instruction documentation rather than as a general hardware-performance rule.
Notes Carried Over From Earlier Study
Interrupts
- Interrupt 0 is the divide-error exception. Its handler can be replaced in an appropriate real-mode environment.
- Interrupt 1 is associated with debugging, including single-step execution controlled by
TF. - The real-mode interrupt vector table occupies
0000:0000through0000:03FF: 1 KiB containing 256 four-byte entries. - The original exercises used
0000:0200through0000:02FFas apparently unused space. That is an assumption about the exercise environment, not a guarantee that an OS or other program will leave it free. - Updating
SSandSPrequires attention to the processor’s special interrupt behavior around stack-segment changes. - When modifying interrupt vectors, protect the update appropriately; clearing
IFmasks ordinary maskable interrupts while the update is in progress.
A Note About INT 7Ch
The original draft described vector 7Ch as a default timer vector and then discussed periodic timer interrupts. That identification is incorrect for the conventional IBM PC BIOS environment: the timer IRQ normally reaches vector 08h. 7Ch is often chosen for a custom handler in assembly exercises. Its meaning depends on the software that installs the vector.
The general timer explanation still applies: a programmable timer, traditionally the PIT in a PC, generates interrupts at configured intervals. A handler can perform periodic work, such as maintaining time or scheduling a small background task, subject to the environment’s rules.
BIOS and DOS Services
INT 10h provides BIOS video services. For the following examples, AH selects the function:
AH=02h: set the cursor position;BHis the display page,DHthe row, andDLthe column.AH=09h: write a character and attribute;ALis the character,BLthe attribute,BHthe page, andCXthe repeat count.
Examples of DOS INT 21h services:
AH=4Ch: terminate the program;ALsupplies the return code, with zero commonly indicating success.AH=09h: display a$-terminated string whose address is supplied inDS:DX.
I/O Ports
Interface chips on expansion cards, the motherboard, and other devices expose registers that the CPU can access. It is useful to think of the addressed device registers as a logical collection of storage locations, while remembering that accesses can have device-specific effects.
In this real-mode discussion, the I/O port address space contains 65,536 possible addresses, from 0 through 65535. IN and OUT transfer data through the accumulator. The examples use AL for byte transfers and AX for word transfers.
An immediate port operand can encode addresses from 0 to 255, as in in al, 20h. Larger port addresses are supplied through DX.
CMOS RAM
The traditional CMOS/RTC device contains clock information and system configuration used by BIOS at startup. These notes consider a device with 128 storage locations. Addresses around 00h through 0Dh contain RTC data and control registers; other locations hold configuration information.
Port 70h selects the CMOS register and port 71h accesses its data.
Shifts
For SHL and SHR, the last bit shifted out is placed in CF. In the 8086 forms studied here, a count greater than one is supplied through CL; later x86 instruction sets also provide immediate-count forms.
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